Ethernet PCS 1G/2.5G
Overview
Comcores PCS IP core is a silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2015. The IP-core supports 1G and 2.5G line rates. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a Gigabit Media Independent Interface (GMII) or Serial Gigabit Media Independent Interface (SGMII). On one side it interfaces to a Serdes device and on the application side it has a port for GMII/SGMII Ethernet signals.
The IP-core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.
Block Diagram
Key Features
Richly Featured
- Configurable for many operating modes
- IEEE Std. 802.3 Clause 37 Auto-negotiation
- BER test option included
- Loopback at both ends
Delivering Performance
- Designed to IEEE 802.3-2015 specification
- Low Latency
- Can be used in synchronous Ethernet applications
Silicon Agnostic
- Designed in VHDL and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
Easy to use
- MDIO Slave PHY Management interface
- GMII/SGMII interfaces for attaching to Ethernet MAC
- User-friendly application interface
Applications
Any 1G/2.5G Ethernet Solution
- Fits into solutions where Eth. PCS is needed
Deliverables
The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.
Please Contact us to discuss your project requirements.
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
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