Ethernet PCS 10G/25G


Comcores 10G/25G PCS IP core is a silicon agnostic implementation of the PCS layer described in the Ethernet standard IEEE 802.3-2015 and compliant with Clause 49 of IEEE 802.3ae specification. The IP-core is part of a family of IP-cores that are tightly intergrated.

The IP-core has been optimized for size and offers an XGMII interface on one side and a 64-bit interface at the PMA-side.

Block Diagram

Ethernet PCS 10G/25G Block Diagram

Key Features

Richly Featured

  • User controlled AutoNegotiation (IEEE 802.3 Clause 37) with full programmability
  • Support for 10G Energy-Efficient Ethernet (EEE) compliant with the IEEE, 802.3az specification
  • Complete 10GBASE-R, 10GBASE-KR and 25GBASE-R PCS solution

Delivering Performance

  • Designed to IEEE 802.3-2015 specification
  • Low Latency
  • Can be used in any 10G or 25G Ethernet PHY application

Silicon Agnostic

  • Designed in VHDL and targeting any RTL implementation like ASICs, ASSPs and FPGAs

Easy to use

  • Seamless connecting to Comcores MAC to build single chip 10G ETH Controller
  • XGMII interfaces for attaching to Ethernet MAC
  • Easy configurable through APB bus
  • Includes test pattern Generator/Checker
  • Configurable for many operating modes and speeds
  • Works with multiple Serdes widths


Any Ethernet Solution

  • Fits into solutions where Eth. PCS is needed

Multi-rate solutions

  • Enabling use of multiple rates of Ethernet


The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.

Please Contact us to discuss your project requirements.

What Comcores IP will do for you


Proven Quality

Solid process and predictability

Strong verification


Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research


Long-term experience in communication protocols

Expert in executing digital design projects

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